Telecommunications, network, and computer applications often require the ability to insert and remove battery equipped systems from accessories. During these operations an undesired short condition can appear on the connector leading to currents of several amperes of peak amplitude, which can damage the circuitry and the battery. To prevent such deleterious effects, protection circuits are coupled to the connector interface and have current limit capabilities that control a power MOSFET switch through which the supply current is routed.
Existing current limiters suffer from a high cost due to the large number of components needed to control the power MOSFET switch in a fashion that limits the current to a specified level. In addition, the use of integrated circuit techniques to limit current flow are unsuitable for use with discrete power MOSFETS because of deficiencies inherent in coupling a discrete power MOSFET to an integrated circuit. For example, FIG. 1 illustrates a prior art current limit circuit 10 in which a switch 12 is coupled to an integrated circuit 14. It should be noted that switch 12 is a discrete component whereas integrated circuit 14 is a monolithically integrated circuit. In other words, switch 12 and integrated circuit 14 are manufactured from two separate silicon substrates. Switch 12 comprises a power MOSFET 16 having a source, a drain, and a gate. Integrated circuit 14 comprises MOSFETS 20 and 22, resistors 24, 26, and 28, an amplifier 30, a comparator 32, and a charge pump 34. Unlike power MOSFET 16 which is manufactured using a semiconductor process tailored for discrete power devices, MOSFETS 20 and 22 are manufactured using a process tailored for integrated circuits. MOSFET 20 has a drain coupled to an input node 36 through resistor 24, a source coupled to a ground potential through resistor 26, and a gate coupled to an output of amplifier 30. Amplifier 30 has an input coupled for receiving a reference potential VREF and an input coupled to the source of MOSFET 20. One input of comparator 32 is coupled to the drain of MOSFET 20 and the other input is coupled to the drain of MOSFET 22 and to one terminal of resistor 28. The other terminal of resistor 28 is coupled to input node 36. The output of comparator 32 is connected to an input of charge pump 34 and the output of charge pump 34 is connected to the gate of MOSFET 22. The source of MOSFET 22 is connected to an output node 38. An output voltage VOUT appears at output node 38.
Switch 12 and integrated circuit 14 are mounted to a support structure such as a printed circuit board and the drain and source of power MOSFET 16 are coupled to input node 36 and output node 38, respectively, and the gate of power MOSFET 16 is connected to the gate of MOSFET 22. Thus the output of charge pump 34 is commonly connected to the gates of power MOSFET 16 and MOSFET 22 and the sources of MOSFET 22 and power MOSFET 16 are connected together.
In operation, amplifier 30 in combination with MOSFET 20, resistors 24 and 26, input voltage VIN at input node 36, and reference voltage VREF generate a voltage V1 at one input of comparator 32. Power MOSFET 16 and MOSFET 22 are configured as a current mirror such that a current I1 flows through power MOSFET 16 when it is on and conducting current and a mirror current I1M flows through MOSFET 22 when it is on and conducting current. Mirror current I1M in combination with resistor 28 and a voltage VIN appearing at input node 36 generate a reference voltage V2 at the other input node of comparator 32. If mirror current I1M is outside a safe operating range, voltage V2 will be less than voltage V1 and comparator 32 generates an output signal that disables charge pump 34. Disabling charge pump 34 turns off power MOSFET 16 and MOSFET 22 thereby limiting the levels of current I1 and mirror current I1M. If mirror current I1M is within a safe operating range, voltage V2 will be greater than voltage V1 and comparator 32 generates an output signal that enables charge pump 34. Enabling charge pump 34 leaves power MOSFET 16 and MOSFET 22 on and conducting current I1 and mirror current I1M. A drawback with this circuit configuration is that power MOSFET 16 and MOSFET 22 are manufactured from different silicon substrates, thus mirror current I1M does not match current I1. This mismatch introduces inaccuracies in the signals from the current mirror circuit and thus in the signals from the current limit circuit that may lead to over-current conditions that can catastrophically damage switch 12, integrated circuit 14, or both. A drawback with manufacturing switch 12 and integrated circuit 14 using the same substrate and the same manufacturing process is that the process requirements would be set by power MOSFET 12. Manufacturing MOSFETS 20 and 22 using a manufacturing process tailored for power MOSFET 16 degrades their performance making them unsuitable in a current limiting application.
Accordingly, it would be advantageous to have a current limit circuit and a method for limiting current that includes the use of semiconductor components manufactured using different process flows without ideal current matching. It would be of further advantage for the circuit and method to be time and cost efficient to implement.